The present invention relates generally to MOSFET transistors and more generally to DMOS transistors having a trench structure.
DMOS (Double diffused MOS) transistors are a type of MOSFET (Metal On Semiconductor Field Effect Transistor) that use diffusion to form the transistor regions. DMOS transistors are typically employed as power transistors to provide high voltage circuits for power integrated circuit applications. DMOS transistors provide higher current per unit area when low forward voltage drops are required.
A typical discrete DMOS circuit includes two or more individual DMOS transistor cells which are fabricated in parallel. The individual DMOS transistor cells share a common drain contact (the substrate), while their sources are all shorted together with metal and their gates are shorted together by polysilicon. Thus, even though the discrete DMOS circuit is constructed from a matrix of smaller transistors it behaves as if it were a single large transistor. For a discrete DMOS circuit it is desirable to maximize the conductivity per unit area when the transistor matrix is turned on by the gate.
One particular type of DMOS transistor is a so-called trench DMOS transistor in which the channel is formed vertically and the gate is formed in a trench extending between the source and drain. The trench, which is lined with a thin oxide layer and filled with polysilicon, allows less constricted current flow and thereby provides lower values of specific on-resistance. Examples of trench DMOS transistors are disclosed in U.S. Pat. Nos. 5,072,266 (Bulucea et al.), 5,541,425 (Nishihara), 5,430,324 (Bencuya), 5,639,676 (Hshieh et al.), 5,316,959 (Kwan et al.), 5,304,831 (Yilmaz et al.) and 5,866,931.
FIGS. 1A and 1B depict one example of a conventional trench DMOS transistor 101. The device is provided with a first trench 103 T1 which is in the active region of the transistor and a second trench 105 T2 which is in the termination region of the transistor.
Referring now to FIG. 1B, which is a cross-sectional view of the device of FIG. 1A taken along the line X-Xxe2x80x2, the trenches reside in a substrate comprising an n+ doped layer 107, an n doped epitaxial layer 109, and a p type diffusion layer 111 of opposite conductivity. An n+ doped epitaxial layer 113 which overlies the p type diffusion layer serves as the source. The bottom of the trenches terminate in the n doped epitaxial layer. An insulating layer of silicon oxide 115 extends over the surface of both trenches. A source electrode 117 extends over the first trench, and a gate electrode 119 extends over the second trench. Both trenches are filled with polysilicon 121 and capped with BPSG 123 (boron phosphorosilicate glass).
In the device depicted in FIG. 1B, the average thickness tox1 of the silicon oxide layer overlying the first trench is equal to the average thickness tox2 of the silicon oxide layer overlying the second trench, that is, tox1=tox2. Devices of this type have at least one drawback that is an artifact of the methodology by which the device is manufactured. In particular, the device is typically subjected to at least two oxidation treatments during its manufacture, the first of which is employed for the removal of damages occurring at the time of silicon etching after formation of the trenches, and the second of which is used to form the silicon oxide layer. As shown in FIG. 1C, these oxidation steps produce a defect 125 in the form of a protrusion of the p type diffusion layer 111 into the silicon oxide layer 115. This defect, often referred to as a xe2x80x9chornxe2x80x9d, occurs in the upper end corner of the sidewall of the trench. The horn terminates in an acute angle. The thickness xe2x80x9cthxe2x80x9d of the silicon oxide layer in the vicinity of the horn will be smaller than the average thickness tox2 of the silicon oxide layer positioned on the sidewall of the trench or on the surface of the p type diffusion layer.
During use, the n type polycrystalline silicon layer 121 that covers the horn and silicon oxide layer functions as a gate and is supplied with a predetermined potential. However, because of the shape of the horn, an electric field between the n type polycrystalline silicon layer and the substrate is concentrated in the vicinity of horn. Since the thickness of the silicon oxide layer in the vicinity of the horn is thin, the breakdown voltage of the silicon oxide layer is greatly reduced in this area.
Several approaches have been suggested in the art for dealing with this problem. One approach, which is disclosed in IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-34, NO. 8, AUGUST, 1987, pp. 1681-P.1687, is directed toward the oxidation conditions of silicon. In this approach, oxidation is conducted at temperatures as high as 1100xc2x0 C. According to the reference, a horn is not produced at these temperatures, and the upper end corner portion on the sidewall of the trench is rounded. Rounding the upper end corner portion on the sidewall of the trench relaxes the concentration of electric field at the portion, and the breakdown voltage of the silicon oxide layer positioned on the upper end corner portion of the sidewall of the trench is purportedly improved. However, this method is disadvantageous in that the use of such high temperatures in the oxidation steps can adversely affect on the structure of the impurity diffusion layers previously formed.
Another approach for avoiding the reduction in breakdown voltage of the silicon oxide layer at the upper corner portion of the sidewall of the trench is disclosed in laid open Japanese Patent Application Nos. 64-57623 and 63-166230. These references disclose a method of rounding the upper end corner portion on the sidewall of the trench by means of chemical dry etching. However, rounding the upper end corner portion on the sidewall trench in this manner is undesirable because, in order to relax the electric field intensity, the radius of curvature xe2x80x9crxe2x80x9d of the corner portion must be increased. This in turn places a lower limit on the size of the device, which is a serious drawback in that it is desirable to minimize the size of the DMOS transistor.
U.S. Pat. No. 5,541,425 (Nishihara) discloses yet another approach which is intended to overcome the problems associated with segments of the gate oxide layer that have been thinned by two-dimensional oxidation. There, a method is disclosed whereby the top corner of the trench is rounded with an additional heavy arsenic implant through the use of an additional mask. However, the methodologies proposed therein are not suitable for a power MOSFET because the floating arsenic portion causes early avalanche breakdown. Moreover, the heavy doped arsenic portion induces silicon defects during subsequent oxidation processes such as sacrificial oxidation and gate oxidation.
U.S. Pat. No. 5,639,676 (Hshieh et al.) discloses a method for making a trenched DMOS transistor using seven masking steps. In accordance with the method, a masking step is used to produce an insulating oxide layer in the termination region which is thicker than the gate oxide layer in the active region of the transistor. However, as with the device depicted in FIGS. 1A-C, devices of this type are prone to reduction in breakdown voltage of the silicon oxide layer at the upper corner portion of the sidewall of the trench due to two-dimensional oxidation of the silicon oxide layer in this area.
There thus remains a need in the art for a trench DMOS device with improved gate oxide integrity and, in particular, a trench DMOS device having a gate oxide layer with improved breakdown voltage. There is also a need in the art for a method for making such a trench DMOS device, which method is applicable to power MOSFET devices. These and other needs are met by the present invention, as hereinafter disclosed.
The present invention relates to methods for creating trench DMOS devices with enhanced gate oxide integrity and, in particular, to trench DMOS devices in which the gate oxide layer has improved breakdown voltage, and to the trench DMOS devices so made.
In one aspect, the present invention relates to trench DMOS devices, and to methods for making the same. The trench DMOS devices comprise a first region (e.g., an n doped epitaxial layer) having a first conductivity type and a second region (e.g., a p type diffusion layer) having a second conductivity type, and have at least first and second trenches which are in communication with the first and second regions. A first electrically insulating layer is disposed over the surface of the first trench and has a mean thickness over the first trench of t1. A second electrically insulating layer is disposed over the surface of the second trench and has a mean thickness over the second trench of t2. The electrically insulating layers typically comprise an oxide such as silicon oxide. The ratio t1/t2 is greater than 1, and is typically at least about 1.2.
The trench DMOS devices made in accordance with this aspect of the invention are particularly useful in power MOSFET applications. In such an application, the first trench may be disposed in the termination region of the transistor and the second trench may be disposed in the active region of the transistor. The presence of the thicker insulating layer in the termination region maintains the breakdown voltage of the insulating layer at an acceptable level, particularly in the vicinity of the upper corner of the trench where two-dimensional oxidation is most likely to produce horns or similar defects in the insulating layer. Moreover, the thicker insulating layer improves the electric field distribution so that avalanche breakdown occurs in the active region of the transistor rather than in the termination region, thus causing breakdown voltage behavior to be more stable and predictable. The thicker insulating layer also improves process control and reduces substrate contamination during processing. The thicker the oxide, the less the dopant can penetrate from the doped polysilicon through the oxide into the substrate region so a thicker oxide can help to reduce the substrate contamination.
In some embodiments of the trench DMOS devices of the present invention, the average thickness of the insulating layer at the bottom of the second trench is also increased, without increasing the average thickness of the insulating layer in the upper portion of these trenches. Trench DMOS devices of these later embodiments have all of the advantages noted above. Moreover, the presence of a thicker insulating layer at the bottom of the trenches in the active region of a power MOSFET reduces penetration of dopant material through the insulating layer and into the p type diffusion layer in this area of the trench, thereby reducing punch-through.
In another aspect, the present invention relates to a method for making trench DMOS devices, and to the devices so made. In accordance with the method, an article is provided which comprises a first region having a first conductivity type and a second region having a second conductivity type. The article has first and second trenches which are in communication with the first and second regions. A first electrically insulating layer is then deposited over the surface of the first trench. The first insulating layer has a mean thickness over the first trench of t1. Next, a second insulating layer is deposited over the surface of the second trench. The second insulating layer has a mean thickness over the second trench of t2. The thicknesses of the two insulating layers are such that, if k is the larger of the two layers and m is the smaller of the two layers, then k/m is greater than 1, and typically is at least about 1.2.
In the various embodiments of the method of the present invention, the differences in thickness of the insulating layer may be achieved by depositing a first insulating layer over the first and second trench, and then depositing at least one mask (e.g., an oxide mask if the insulating layer is an oxide such as silicon oxide) over at least a portion of the first insulating layer, thereby defining a masked region and an unmasked region. In some embodiments of the method of the present invention, the masked region extends over the entire surface of the first trench, and the unmasked region extends over the entire surface of the second trench. In other embodiments, the masked region extends over the entire surface of the first trench and over a first portion of the surface of the second trench (e.g., the bottom), and the unmasked region extends over a second portion of the surface of the second trench. Any portion of the first insulating layer extending into the unmasked region is then removed, as by etching, and a second insulating layer having an average thickness t2, wherein t1xe2x89xa0t2, is deposited over the unmasked region. Typically, if the first trench is located in the termination region of the transistor and the second trench is located in the active region of the transistor, then t1 greater than t2 This method may be used advantageously to produce a trench DMOS device of the type described above.
In yet another aspect, the present invention relates to an intermediary article which is useful in the construction of a trench DMOS transistors and similar devices, and to methods for making the same. The article comprises a first region having a first conductivity type and a second region having a second conductivity type. A first trench, which is in communication with the first and second regions, has first and second walls and terminates in a first bottom. The first wall extends from the first bottom to a surface of the article, and the intersection of the first wall and the surface defines a first locus. A second trench, which has third and fourth walls and terminates in a second bottom (the second bottom defines a second locus), also extends through the first and second regions. An electrically insulating material (typically an insulating oxide such as silicon oxide) is disposed over at least the first locus. In some embodiments, the insulating material extends over the second locus as well. The article is further provided with at least one mask which defines a masked region and an unmasked region. The masked region extends over the first locus and, in some embodiments, extends over the second locus as well. The unmasked region extends over all areas outside of the masked region, and typically includes at least a portion of the third and fourth walls of the second trench.
The intermediary articles of the present invention may be used advantageously in the manufacture of the trench DMOS transistors and devices of the present invention, as by removing any insulating material present in the unmasked region (as, for example, by chemical etching, where the insulating material is silicon oxide and the at least one mask is an oxide mask) and then depositing another portion of the same or different insulating material over the unmasked region (either before or after removal of the at least one mask). In this way, the thickness of the insulating material (which may form the gate oxide layer and/or a sacrificial oxide layer) may be varied independently over the masked and unmasked regions of the trench DMOS device so as to obtain the benefits described above.